1. Technical Field
Example embodiments relate to methods of forming wiring structures. More particularly, example embodiments relate to methods of forming wiring structures effective for reducing parasitic capacitance.
2. Description of the Related Art
As semiconductor devices continue to become more highly integrated, the size of wirings, or interconnects, and the size of spacing between wirings in a semiconductor device continues to become more considerably decreased. It is generally preferred that the wiring in a semiconductor device have the property of low resistance even though each generation of wiring may have a greatly reduced width. As a result, in contemporary devices, wiring is generally formed using metal having the property of low resistance, such as copper (Cu).
When low-resistance metal wiring structures are arranged at a small spacing, or interval, the parasitic capacitance between adjacent metal wiring structures can be considerably increased. To reduce the parasitic capacitance between metal wiring structures, an insulation layer can be provided between the wiring structures, formed, for example, of a material having a low dielectric constant (i.e., a low-k material). However, this approach is limited in its effectiveness with deeper device integration.